A 700-MS/s 6-bit SAR ADC with partially active reference voltage buffer
نویسندگان
چکیده
منابع مشابه
A 12 bit 76MS/s SAR ADC with a Capacitor Merged Technique in 0.18µm CMOS Technology
A new high-resolution and high-speed fully differential Successive Approximation Register (SAR) Analog to Digital Converter (ADC) based on Capacitor Merged Technique is presented in this paper. The main purposes of the proposed idea are to achieve high-resolution and high-speed SAR ADC simultaneously as well. It is noteworthy that, exerting the suggested method the total capacitance and the rat...
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ACKNOWLEDGMENTS I would like to express my sincere and deep appreciation to my academic advi-sors, Dr. Gabor C. Temes and Dr. Un-Ku Moon, for the research project and excellent academic environment they provided for me. I have been honored and privileged to have worked under their supervision. Without their warm encouragement and academic guidance as well as their generous support, it would be ...
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ژورنال
عنوان ژورنال: IEICE Electronics Express
سال: 2018
ISSN: 1349-2543
DOI: 10.1587/elex.15.20180497